An improved GGNMOS triggered SCR for high holding voltage ESD protection applications
Time to say farewell to the snapback ggNMOS for ESD protection – SOFICS – Solutions for ICs
PDF) Snapback circuit model for cascoded NMOS ESD over-voltage protection structures
Figure 1 from A Method to Prevent Strong Snapback in LDNMOS for ESD Protection | Semantic Scholar
A double snapback SCR ESD protection scheme for 28 nm CMOS process - ScienceDirect
Snapback and the ideal ESD protection solution (Electrostatic Discharge)
Figure 1 from Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration | Semantic Scholar
Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations | Semantic Scholar
Electronics | Free Full-Text | Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs
High Voltage Tolerant ESD Protection Circuit for Plug and Play Devices
The Transistor: An Indispensable ESD Protection Device - Part 2 - In Compliance Magazine
Electronics | Free Full-Text | The ESD Characteristics of a pMOS-Triggered Bidirectional SCR in SOI BCD Technology
MODELING NMOS SNAPBACK CHARACTERISTIC USING PSPICE 1. Introduction 2. NMOS SNAPBACK
Technical considerations and protection mechanism for ESD event...
Snapback behavior determines ESD protection effectiveness - SemiWiki
Figure 1 from Snapback Breakdown Dynamics and ESD Susceptibility of LDMOS | Semantic Scholar
PDF) Modeling snapback of LVTSCR devices for ESD circuit simulation using advanced BJT and MOS models | Yuanzhong Zhou - Academia.edu
Technical considerations and protection mechanism for ESD event...
A double snapback SCR ESD protection scheme for 28 nm CMOS process - ScienceDirect
Bipolar effects in snapback mechanism in advanced n-FET transistors under high current stress conditions
Electronics | Free Full-Text | The ESD Characteristics of a pMOS-Triggered Bidirectional SCR in SOI BCD Technology
GGNMOS ESD Protection Simulation
Bipolar effects in snapback mechanism in advanced n-FET transistors under high current stress conditions
